1. Field of the Invention
The present invention relates in general to integrated circuit crosspoint arrays and in particular to a crosspoint array having a folded layout and multiple levels of switch control.
2. Description of Related Art
A typical crosspoint array implemented on an integrated circuit has several signal ports and can selectively route signals between its ports. The prior art crosspoint array is made up of switch cells arranged in rows and columns and sets of parallel input/output (I/O) lines running both horizontally and vertically through the switch cells for conveying signals to and from the ports. Each vertical I/O line runs through a separate column of switch cells and each horizontal I/O line runs through a separate row of switch cells such that each switch cell lies at the intersection of one vertical I/O line and one horizontal I/O line. Each switch cell includes a switching element such as a pass transistor for selectively interconnecting the horizontal and vertical I/O lines so that signals may pass therebetween. Each switch cell also includes a single bit memory cell storing a data bit for controlling the state of the switch. External control circuits transmit the data bits to the memory cells of each column through "bit" lines extending through each column of the array. The external control circuits also transmit write enable signals to the memory cells in each row via "word" lines extending along each row of the array.
In a square crosspoint array, each horizontal and each vertical conductor services a separate port, and a switch cell is located at every horizontal and vertical I/O line intersection. While a square array is compact in relation to the number of ports it services, it may require a signal to travel through two pass transistors as it travels between ports. Pass transistors slow signal transit and increase signal degradation. In a triangular crosspoint array, hardwire connections between vertical and horizontal I/O lines replace switches along a main diagonal of the array and switches to one side of the diagonal are eliminated. Each interconnected horizontal and vertical pair of I/O lines services a separate port. A triangular crosspoint array makes relatively inefficient use of the surface area of an integrated circuit on which the device is formed since it services only half as many ports as a rectangular array of similar size. However the triangular crosspoint array routes signals between any two ports through only a single pass transistor. Thus triangular crosspoint arrays permit faster signal transit with less signal degradation.
A triangular crosspoint array, for example having 32 input/output ports, could be used to selectively interconnect bi-directional buses. One eight-bit bus from a computer could be connected to eight of the 32 ports while three eight-bit buses from peripheral devices could be connected to the other 24 input/output ports. The crosspoint array could then be configured to connect the computer to any selected one of the peripheral devices at any time. One disadvantage of using a conventional triangular crosspoint array to switch buses is the speed with which it can change signal routing. Data is written to one row of cells at a time and many clock cycles are needed to reconfigure switching patterns. Since the time required to reconfigure a crosspoint array can be relatively long, crosspoint arrays are not often used for bus switching.
What is needed is a large crosspoint array that requires minimal surface area of an integrated circuit, which routes signals between ports via only a single pass transistor, and which can rapidly switch busses connected to its ports.